1. Field of the Invention
The present invention relates to a method for manufacturing a transistor, and more particularly, to a method for manufacturing a transistor capable of improving matching among transistors (e.g., on a wafer, from wafer-to-wafer, and/or from lot-to-lot) or among structures in a transistor.
2. Discussion of the Related Art
In a general driving circuit for a flat panel display such as an LCD, a PDP and an OLED which are recently growing in the market, a high-voltage device and a low-voltage device are integrated in one chip. Such a circuit is called a high-voltage integrated circuit. In order to design the high-voltage integrated circuit, models of a high-voltage metal oxide semiconductor (MOS) transistor and a low-voltage complementary MOS (CMOS) circuit transistor are useful.
FIG. 1A to FIG. 1D are sectional views showing the processes for forming a general drain-extended MOS (DEMOS) transistor.
Referring to FIG. 1A, active regions (for example, p-wells; not shown) are defined on a semiconductor substrate 10. After a barrier oxide layer 35 and a nitride layer (not shown) are vapor-deposited on the active regions, an isolation layer (not shown) is formed by shallow trench isolation (STI) to separate the respective active regions.
Next, a photoresist pattern 40 is formed by performing photolithography, and a drift region 45 is formed by performing a lightly doped drain (LDD) implantation using the photoresist pattern as a mask.
As shown in FIG. 1B, next, post-ion implant cleaning and annealing are performed, thereby activating cohesion between the implanted dopants and silicon atoms.
A gate oxide layer 50 is grown on the semiconductor substrate 10. Polysilicon is deposited (e.g., by vapor-depositing) on the gate oxide layer 50. A poly gate 60 is formed through photolithography and etching processes.
After this, spacers 70 are formed on sidewalls of the poly gate 60. Source and drain regions 80 are formed a predetermined distance from the poly gate 60 by ion implantation.
As shown in FIG. 1C, an oxide and/or a nitride is vapor-deposited on the whole surface of the resultant structure, and a photoresist pattern is formed on the oxide and/or nitride through photolithography using a non-silicide mask to expose parts of the oxide and/or nitride excluding a silicide region that will be formed later. In addition, a silicide barrier layer 90 is formed by etching the oxide or nitride by using the photoresist pattern as a mask.
Next, as shown in FIG. 1D, the photoresist pattern is removed and a silicide is vapor-deposited on the whole surface of the resultant structure. Additionally, a thermal processing and annealing are performed to form a silicide layer 95.
However, when the drift region formed by LDD implantation is used in the general DEMOS transistor, matching characteristics may deteriorate when the device size is increased. Furthermore, in the case of a device used in an electrostatic discharge (ESD) circuit, a non-silicide process including a non-silicide masking operation generally improves the ESD characteristics.